The present exemplary embodiments pertain to bulk FinFET devices and, more particularly, pertain to bulk silicon germanium (SiGe) FinFET devices that may avoid certain dislocation just below the SiGe fins.
SiGe fins in a bulk FinFET have been touted as a viable option to improve PFET performance.
FIG. 1 is a plan view of a prior art bulk SiGe FinFET. FIG. 2A is a cross-sectional view of FIG. 1 in the direction of arrows A-A and FIG. 2B is a cross-sectional view of FIG. 1 in the direction of arrows B-B.
FIGS. 2A and 2B illustrate a bulk silicon substrate 10 have fins 12 extending from the bulk silicon substrate 10. The fins 12 include a silicon bottom part 14 and a SiGe top part 16. Silicon bottom part 14 of fins 12 may include a punchthrough stop 18. Insulation between the fins 12 is provided by shallow trench isolation 20. Wrapping around the SiGe top part 16 is a gate dielectric 22 and gate 24. As best seen in FIG. 2B, there is a source 26, drain 28 and gate spacers 30.